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This project concentrates on developing highly integrated power efficient design algorithms for custom and application specific systems. Particularly of interest is embedded Multiprocessor Systems on Chip (MPSoC).
Multiprocessor System-on-Chip (MPSoC) is becoming a major system design platform for general purpose and real-time applications, due to its advantages in low design cost and high performance. Minimizing the power consumption is one of the major issues in designing battery operated MPSoC. The massive performance boost gained by parallel architecture over uniprocessor systems can be explored to develop new algorithms and transformed into power reduction through power reduction techniques such as voltage scaling.
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Flexible electronics, also known as flex circuits or flex circuit board, is a new technology for building electronic circuits by depositing electronic devices on flexible substrates such as plastic, cloth, and paper.
It is thin, light-weighted, and unbreakable. It is also low-cost due to cheaper material and cheaper manufacturing processes. It takes variable forms in different applications, for example, Radio Frequency Identification Tag (RFID), flexible displays, and integrated analog/digital systems. Basic devices for building flex circuits are OTFT (Organic Field-Effect Transistor), OLED (Organic light-emitting diode), a-Si (Amorphous silicon), and etc.
Due to the features of low mobility, large power supply, threshold voltage shift or instability of the new flex devices, innovative circuit design methodologies are required to build applicable and low-power Flex circuit systems. Our research focuses on electrical characteristics of OTFT, proposing new design techniques for compensating its drawbacks, circuit simulations, and seek collaboration in manufacturing actual flex circuits.
Power consumption has become one of the major roadblocks in the VLSI technology. Dynamic power management (DPM) is an effective and well-developed method to control the system power at the system level. It selectively shuts off or turns down some of the system components that are idle or underutilized. Most of the models for DPM are based on Markov decision process (MDP). However, as the hardware and software complexity grows, it is unlikely for the power management hardware/software to have a full observation of the entire system status. Our research focuses on the power management of a partially observable system, in which some of the system states cannot be observed when the power manager makes decisions. We propose a new modeling and optimization technique based on partially observable Markov decision process (POMDP) to find the optimal policy for robust power management in a partially observable environment.
Most of DPM methodologies have been developed based on single core system. However, architecture shifting from single-core to multi-core in nowadays system design is an inevitable trend. Complexity of dynamic power management in multi-core system increases dramatically, and previous DPM methodologies can not fit in with new applications. So new methodologies for multi-core system must be researched and developed.
Our DPM methodology for multi-core/multi-processor system is to appropriately schedule tasks such that idle time interval in each processor is maximized and switching overhead of DPM is minimized. A control-data flow graph (CDFG) is used for capturing data dependencies between different tasks. In order to schedule a task, its slack is first calculated. If its successor(s)/predecessor(s) share(s) the same processor, and their slacks overlap with each other, then these two tasks are scheduled to be executed continuously by the processor. In the upcoming task scheduling, these two tasks are regarded as a new single task with new predecessor(s)/successor(s). Task scheduling stops until no more tasks can be executed continuously. Simulation results show our methodology significantly reduces the overhead of dynamic power management. Specifically, the overhead goes down by 56% on average.
Cognitive computing would be important in many practical computer applications in the next few decades. Some applications include a) Language understanding b) Internet searching c) Cognitive data mining d) Pattern recognition etc. These applications would be more efficient on hardware with brain-like architecture. Research requires,
Our research involves implementing Brain-State-in-a-Box (BSB) models in hardware which is speculated to that of a single cortical minicolumn in the striate cortex. The BSB model is able to recognize the trained pattern reliably. BSB models have to be combined with inter BSB communication to form the cortex for larger applications such as pattern recognition. One other application using a single BSB model is the word disambiguation, where the neural network removes the ambiguity of the word meanings by using the context.
Recent research has shown that DNA codewords can be used for solving hard combinatorial problems. However, the success of such a DNA-computer largely depends on huge and reliealbe DNA codeword library and DNA codeword searching is one of the NP-hard problems. Through this project we propose a hybrid architecture for accelerating the DNA codeword library searching using Genetic Algorithm(GA), which consists of a host PC and a hardware accelerator implemented in Field Programmable Gate Array (FPGA). With a single instance of GA , the proposed architecture shows speed up of 1000x compared to a software only implementation for DNA codeword with 16 bases. Implementation with two instances of GA shows a linear speedup compared to single instance implementation
Since reliability is one of the major issues with DNA codeword libraries, we are investigating different metrics for estimating the binding strength of DNA pairs like Thermodynamics. In future we intend to extend the current architecure for generating DNA codewords of length 32 and more
Leakage current estimation is not a trivial task in low power logic circuit design any more. As we know, current cut-edging CMOS technology is in the range of tens of nano-meter, and leakage power becomes a significant contributor to the full-chip power consumption. Under the nano-scale CMOS technology, process variation has dramatic impact on transistor parameter values, resulting in the full-chip leakage is not deterministic. In essence, the full-chip leakage is a random variable under process variation, and it is subject to some distribution. In order to have good understanding of the full-chip leakage and figure out some effective ways to reduce it, we need to know what that distribution is exactly. Many of previous works have obtained that distribution based on probabilistic theory; however, some critical approximations in their derivations degrade the accuracies of results. In our work, a sampling technique is used and it can nearly fully capture the relationship between full-chip leakage and process variation. The larger the sample size, the higher the accuracy of result. The full-chip leakage distribution can also be derived based on the given confidence level and error violation level. Simulations show that our proposed sampling technique is an effective way to estimate leakage and its distribution under process variation. In addition to that, it also reduces the complexity of leakage and its distribution estimation, compared to the previous works.